`include "defines.v"
module LLbit_reg(
	input wire clk,
	input wire rst,
	input wire exception, //异常信号
	input wire wData_i,
	input wire wCe_i,
	output reg data_o

);
	always@(posedge clk)
		if(rst == `RstEnable)
			data_o <= 1'b0;
		else if(exception == `Exception_Happen)
			data_o <= 1'b0;
		else if(wCe_i == `WriteEnable)
			data_o <= wData_i;
endmodule